Keep pulling the thread on David Kravitz.
Architectural advancements in SiFive's technology allow its next-generation chips to deliver server-class AI performance in a small, ultra-efficient physical footprint.
SiFive's SmartFlow technology uses transfer buffers to move operands and results between the scalar and vector units, preventing pipeline stalls.
SiFive's architecture uses a unique 'global ID' for each instruction to coordinate data transfers between its separate scalar and vector units.
The creators of the RISC-V ISA, Krste Asanović and Andrew Waterman, are founders of SiFive.
David Kravitz is a co-inventor on several patents that power the SiFive SmartFlow technology.
SiFive SmartFlow technology is a feature within SiFive's performance family of products.
SiFive's processor architecture features a scalar out-of-order unit and a vector out-of-order unit that operate with limited knowledge of each other's activities.
The ARM vector architecture utilizes the same architectural registers for both floating point and SVE operations.
Using unified registers for different operation types, as ARM's architecture does, limits flexibility and the amount of work that can be done out-of-order.
The SiFive P570 processor has 128-bit wide vector registers.
Implementing out-of-order execution with multiple physical registers for each architectural register becomes prohibitively expensive for very wide vector registers, such as 1K or 2K bits.
The SiFive P570 and P870D processors are designed as application processors intended to run in a Linux environment.