Sequoia Capital AI Ascent 2026• May 6, 2026• 10:30ConferenceKeynote

AI That Designs Its Own Chips: Ricursive's Anna Goldie and Azalia Mirhoseini

From Sequoia Capital AI Ascent 2026 · 2026

Anna Goldie•Co-Founder, Recursive Intelligence

Executive Summary

Recursive Intelligence, founded by the creators of Google's Alpha chip project, is using AI to automate and optimize the semiconductor design process.
The company's core technology aims to make chip design tools up to 100,000 times faster, enabling a recursive loop where better AI designs better chips for AI.
Their long-term vision is to usher in a "designless" era, becoming a platform that democratizes custom chip creation, similar to how TSMC enabled the "fabless" model.
The company has a three-phase strategy: first, accelerating design for existing chipmakers; second, becoming a platform for workload-specific chips; and third, vertically integrating to build their own chips and AI models.

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Concerns Raised

The economic viability of producing a wide variety of specialized chips at scale compared to mass-produced general-purpose chips.
Overcoming the inertia of deeply entrenched workflows and commercial EDA tools within the semiconductor industry.
Executing an ambitious three-phase strategy that requires evolving from a software tools company to a vertically integrated hardware and AI provider.

Opportunities Identified

Dramatically reducing chip design cycles, which has a massive economic impact, as a one-day delay for a major chip can cost over $200 million.
Democratizing custom silicon for any company with a large-scale AI workload, not just hyperscalers.
Creating a new industry standard with a "designless" platform, capturing significant value in the semiconductor ecosystem.
Unlocking new levels of performance and efficiency through AI-driven co-design of hardware and software.

Key Themes

AI for Chip Design

The core thesis is that neural networks, particularly reinforcement learning, can replace traditional tools and human expertise in the semiconductor design process. This approach, proven with the Alpha chip project on Google's TPUs, can generate superhuman, optimized chip layouts.

This represents a paradigm shift in electronic design automation (EDA), promising to drastically reduce time-to-market, lower costs, and improve chip performance, power, and area (PPA).

The 'Designless' Era

Recursive Intelligence aims to create a new industry model analogous to the 'fabless' revolution enabled by TSMC. By providing a platform that abstracts the complexity of chip design, they would allow any company with a significant computational workload to create custom silicon without needing a large in-house design team.

This could democratize access to high-performance, application-specific hardware, potentially leading to a 'Cambrian explosion' of diverse and specialized chips beyond the current offerings from major players.

Recursive Self-Improvement

The company's name reflects their goal of creating a virtuous cycle between AI and hardware. By using AI to design more efficient chips, those new chips can then be used to train and run more powerful AI models, which in turn can design even better chips.

This feedback loop has the potential to accelerate progress in both AI capabilities and semiconductor technology at an exponential rate, fundamentally altering the economics of compute.

Multi-Phase Vertical Integration Strategy

The company outlines a clear, ambitious three-phase plan. Phase one focuses on providing tools to accelerate existing chipmakers. Phase two involves becoming a platform for designing custom chips based on workloads. The final phase is full vertical integration, where they would design their own chips to train and serve their own proprietary AI models.

This long-term strategy shows a clear path from being a tool provider to a dominant, vertically integrated AI company, controlling the entire stack from silicon to intelligence.

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Topics

Recursive Intelligence AI for Chip Design Semiconductor Design Electronic Design Automation (EDA)Reinforcement Learning Alpha chip Google TPU Vertical Integration Fabless Model Designless Model Custom Silicon AI Accelerators Static Timing Analysis (STA)Chip Layout Time-to-Market

Processed May 10, 2026 yt-dlp + mlx-whisper + Gemini

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